Since a silicon CMOS logic gate device has both ultra large-scale integration and ultra low power consumption performances, it forms a core of the current semiconductor integrated circuit technology. As in a configuration example of the logic gate device in the prior-art technology shown in FIG. 6, in the CMOS logic gate, by combining and complementarily operating an n-type channel MOSFET (metal oxide film semiconductor type electric field effect transistor) and a p-type channel MOSFET, such a characteristic is provided that an operating current does not flow when an input/output logic level is a low level or a high level, and the operating current flows only while the logic level is in transition as an operating current/output voltage characteristic shown in FIG. 7. This fact gives the ultra low power consumption performances. Usually, in the MOSFET, an n-type semiconductor and a p-type semiconductor are formed by doping donor and acceptor impurities by a so-called channel doping technology.
Hitherto, by reducing a distance and time in which an electron/hole runs between electrodes by means of miniaturization of an element, speed-up of a transistor FET and hence, a logic gate device has been promoted. However, in recent years when a characteristic dimension of the FET (electric field effect transistor) is approaching 10 nm at which a quantum-mechanical tunnel effect might be incurred, it has already become difficult to achieve speed-up by miniaturization of an element. Therefore, introduction of a material excellent in carrier transport property which can transport an electron/hole at a higher speed than a semiconductor material including silicon currently in use is a method left for speed-up.
With such a background, a single-layer sheet of carbon forming a hexagonal lattice structure: graphene is far more excellent in electron transport property than any existing semiconductor and attracts attention as a new semiconductor material which can drastically improve a speed performance of transistor performances faced with a limitation of miniaturization. As for graphene, the highest point in the valence band is present at the K point, which borders with the lowest point of a conduction band. That is, there is no band gap. At the same time, since both the conduction band and the valence band have symmetric linear dispersion property in the vicinity of the K point, an effective mass does not exist either in electron/hole and thus, electron mobility is higher than the prior-art semiconductor material by one digit or more and hole mobility is also equivalent, which is an excellent carrier transport property that cannot be realized by the prior-art semiconductor material (See Non-Patent Documents 1, 2, and 3, for example).
However, graphene cannot realize a logic operation equivalent to CMOS by substituting MOSFET as it is due to the following two points. The first point is that since doping of impurities is extremely difficult, it is only a so-called intrinsic semiconductor characteristic that can be provided, and realization of an n-type or p-type semiconductor characteristic having sufficient carrier concentration is extremely difficult (See Non-Patent Documents 1, 4, and 5, for example). The second point is that since a band gap is not present and an electron/hole is present equally in graphene, an operation as an FET has a so-called ambipolar characteristic (single pole bilateral characteristic) having both a region operated in an electron mode when a gate bias is higher than a gate threshold potential and a region operated in a hole mode when the gate bias is lower than the gate threshold potential. Therefore, even if the gate bias falls below the threshold value, the FET is not brought into an OFF state (See Non-Patent Documents 6, 7, 8, and 9, for example). Due to the above reasons, in a FET having a graphene material as an electron channel layer (channel), a configuration of a CMOS logic gate composed of a p-type channel FET and an n-type channel FET is impossible, and thus, a configuration of a CMOS-compatible complementary gate which can realize the current ultra low power consumption and super large integration has been impossible.